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CT2565 Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
I I I I I I I I I I I
Second Source Compatible to the BUS-65600 RTU implements all dual redundant mode codes Selective mode code illegalization available 16 bit microprocessor compatibility BC checks status word for correct address and set flags RTU illegal mode codes externally selectable 16 bit Processor compatibility DMA handshaking for subsystem message transfers MIL-PRF-38534 compliant circuits available DESC SMD #5962-88585 Pending Packaging - Hermetic Metal * 78 Pin, 2.1" x 1.87" x .25" Plug-In type package * 82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
A E RO
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ISO 9001
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RTIFIED
B
S
I NC .
General Description
The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus Monitor (BM). The CT2565 is compatible with most processors. It provides a 16 bit three-state parallel data bus and uses direct memory access (DMA type) handshaking for subsystem transfers. All message transfer timing as well as DMA and control lines are provided internally. Subsystem overhead associated with message transfers is therefore minimized. Interface control lines are common for both BC and RT operation. The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode codes. In addition, any mode code may (optional) be illegalized through the use of an external (200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU operation. Error detection includes: response time-out, inter message gaps, sync, parity, Manchester, word count and bit count. The CT2565 complies with all the requirements of MIL-STD-1553. The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the full military temperature range of -55C to +125C. eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT2565 REV B 8/10/99
STATUS INPUTS
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RTADDR
DBACCEPT SSFLAG SERREQ SSERR SSBUSY
MODE CODE CONTROL CH A CONTROL REMOTE TERMINAL LOGIC
TXINH A TXDATA A TXDATA A RXDATA A RXDATA A
CH A ENCODE/ DECODE
WC0-WC4 T/R LMC ILLCMD
I/O0 - I/O16 DATA BUFFERS
DATA BUS
BUFENA
R/W
EN
2 CH B CONTROL CONTROL BUS BUS CONTROLLER LOGIC I/O BUS I/O LOGIC BUFFERS PARITY CHECKER
TXINH TXDATA TXDATA RXDATA RXDATA
B B B B B
CH B ENCODE/ DECODE
RTADDR
RTADR0 RTADR1 RTADR2 RTADR3 RTADR4 RTADRP
RTADDR
BUSREQ BUSGRNT BUSACK TIMEOUT SOM EOM INCMD CS OE WR TESTIN TESTOUT RT/BC MT BCSTART CHA/CHB LOOPERR MSGERR STATERR LWORD HSFAIL STATEN BITEN NBGRNT ADRINC NODT BSCTRCV
12MHz
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Figure 1 - CT2565 Block Diagram
Values at nominal Power Supply Voltages unless otherwise specified PARAMETER Logic VIH VIL VOH VOL IIH IIL IOL * IOH * CIN (f = 1MHz) COUT (f = 1MHz) Power Supply +5VDC Tolerances Supply Current Internal Decoupling Temperature Range Operating (Case) Storage Physical Characteristics Size 78 pin DDIP 82 pin flatpack Weight VALUE 2.0 min 0.8 max 3.7 min 0.4 max 100 max -0.4 max 1.2 max 0.4 max 20 max 20 max UNITS V V V V A mA mA mA pF pF
10 max 50 typ (70 max) 1.5 typ
-55 to +125 -65 to +150
% mA F C C
1.9 x 2.10 x 0.25 (48.30 x 53.34 x 6.35) 1.6 x 2.19 x 0.15 (40.64 x 55.63 x 3.81) 1.7 (48)
in (mm) in (mm) oz (g)
* I OL and IOH parameters are indicated for all logic outputs except Data Bus (DB0 - DB15) which are 5mA for both parameters.
Table 1 - CT2565 Specifications
GENERAL The CT2565 uses a custom CMOS ASIC for protocol logic and I/O buffering to provide low power dissipation in its small package. The CT2565 performs a continuous on-line Built-In-Test (BIT); in this test the last transmitted word of each message transfer is wrapped around through the active receiver channel and verified against the captured encoded word. A user-defined loop test under subsystem control can also be implemented. Numerous error flags are provided to the subsystem including message error, status error, response time out and loop test error. An external 12 MHz, TTL clock connected to Pin 39 is required. Where appropriate, references to signal names and their associated pin numbers for the 78 pin
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DDIP package are made throughout this document. For flatpack model pin numbers, refer to Table 10. BC/RTU/MT Initialization The CT2565 provides BC, RTU, and MT operating modes. The operating mode if dynamically selectable through two static control inputs as listed in Table 2. It is recommended that a master RESET signal be issued (80ns min) prior to mode selection to clear the internal registers.
MIL-STD-1553 Word Types Figure 2 illustrates the three MIL-STD-1553 word types: Command, Data, and Status.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
BIT TIMES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
COMMAND WD SYNC
5 REMOTE TERMINAL ADDRESS T/R
5 SUBADDRESS MODE 16
5 DATA WORD COUNT/MODE CODE
1 P
DATA WORD SYNC STATUS WORD SYNC 5 REMOTE TERMINAL ADDRESS 1 1
1 P 3 RESERVED PARITY TERMINAL FLAG DYNAMIC BUS CONTROL ACCEPTANCE SUBSYSTEM FLAG BUSY BROADCAST COMMAND RCVD 1 1 1 1 1 1
DATA 1
MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST Note: T/R - Transmit/Receive, P - Parity
Figure 2 - MIL-STD-1553 Word Types
RT/BC (PIN 1) 0 1 0 MT (PIN 2) 1 1 0
MODE BC RT MT
triggers an address increment (ADRINC pin) low output pulse used to increment the subsystem memory address for successive transfers. BC OPERATION In the BC mode, the CT2565 initiates all MIL-STD-1553 data and control message transfers. Figure 3 details specific message transfer flow and Table 3 lists subsystem memory allocation. The subsystem, or host processor, must provide a CT2565 protocol Control Word (See Figure 4) and MIL-STD-1553 command and data words. The CT2565 will transfer the RTU status response and provide message transfer validation during an active transfer. All parallel word transfers occur in the form of a DMA (request-grant-acknowledge) handshake with memory read or operation as shown in Figures 5 and 6. Command Transfer In the BC mode pulse BCSTART (pin 41) low. Following the pulse, the CT2565 will initiate a DMA handshake and memory read for; the control, word, command word(s) and up to 32 data words. No handshake timeout is enforced in the BC mode (CT2565) remains idle during BUSREQ to BUSGRNT), however 1553 protocol must be maintained.
Note that commands are named from the BC's point-of-view (for example, a TRANSMIT CMD indicates the addressed RTU must transmit data).
Table 2 - Operating Modes
DMA - Type Handshake All BC and RT word transfers are preceded by a request-grant-acknowledge format DMA handshake procedure. Timing information is provided in BC, RTU and MT sections. In MT mode, the 1553 transmission is transferred along with an identification Word using a single DMA handshake containing two memory-write operations. The DMA format requires that the subsystem provide a bus grant (BUSGRNT pin 45) low within a timeout period. Note that BUSGRNT should be set to logic "1" before another bus request (BUSREQ) is issued. Memory Read/Write With the single exception of an RT command word transfer, all subsystem transfers take the form of a static memory read or write. A low pulse on both the chip select (CS) and output enable (OE) or a low pulse on CS and write enable (WE) (pins 17, 18 and 44 respectively) indicates data is valid on the parallel data bus for the duration of the pulse. The rising edge of CS
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
RECEIVE Control Word Receive Command Data 1 * * Last Data Looped Data Word RTU Status
TRANSMIT Control Word Transmit Command Looped Command Word RTU Status Data 1 * * Last Data
Table 3 - BC Memory Allocation
Loop Test Upon receipt from the subsystem, the last word to be transmitted within a given message transfer (command or Data word) is stored in a CT2565 internal register. As this word is transmitted to the 1553 bus, it is looped back through the active receiver channel for auto-BC, Short Loop verification. A LOOPERR (.5us typ) low pulse indicates a mismatch between the stored and looped word. The CT2565 also initiates a handshake with a memory write to the subsystem for user-defined, "long loop" (subsystem, CT2565, subsystem) verification. Note that both short and long loop testing are initiated for all transfers (on the last word transmitted to 1553). Subsystems response to use Long Loop Test is to compare the loaded word to what was looped back into memory.
15
NOT USED BUS CHANNEL A/B NOT USED MASK BROADCAST BIT NOT USED MODE CODE BROADCAST RT-RT
8
0
BIT BUS CHANNEL A/B
DEFINITION When logic "1" transmits over 1553 Bus A. When logic "0" transmits over 1553 Bus B (See note) Always set to "0" Command Word count field signifies mode code type Multiple RTU's addressed, no status word expected When set, RTU(b) transmits, RTU(a) receives. Both RTU Status Words are validated and sent to subsystem.
MASK BROADCAST BIT MODE CODE BROADCAST RT-RT
Note: Messages-transmission (routing) status pin (pin 16, Chan A/B) becomes active after loading the control word and command word respectively. The signal is cleared by RESET or EOM low.
Figure 4 - BC Control Word
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
CONTROL & COMMAND WORDS
START BC OPERATION
DATA WORDS
A
NO
RX CMD
YES
HANDSHAKE (DMA) SHORT LOOP HANDSHAKE (DMA)
MEMORY READ CONTROL WORD FROM SSIU NO INCREMENT MEM ADDR OUTPUT
LONG LOOP
MEMORY READ DATA WORD FROM SSIU
STATUS FROM RT YES HANDSHAKE (DMA)
INCREMENT MEM ADDR
DATA TO 1553
HANDSHAKE (DMA)
MEMORY WRITE STATUS WORD TO SSIU
MORE DATA NO SHORT LOOP
YES
MEMORY READ COMMAND WORD FROM SSIU
STATERR
INCREMENT MEM ADDR
LONG LOOP
NO CMD WORD TO 1553 TIMEOUT MSGERR
STATUS FROM RT YES HANDSHAKE (DMA)
STATUS FROM RT YES STATERR
NO
A
TIMEOUT MSGERR
MEMORY WRITE DATA WORD TO SSIU
MEMORY WRITE STATUS WORD TO SSIU
MORE DATA NO
YES
END OF MESSAGE PULSE
Notes: (1) Steps marked with " _ _ _" indicates operation is transparent to user. (2) Steps marked with " ___" indicates user interaction required.
STOP
Figure 3 - BC Message Transfer Flow
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
TRANSFER/CONDITION
CONTROL/COMMAND WORD 1 Handshake Failure LOOPED WORD Short Loop Failure Long Loop Failure RT-RT
DESCRIPTION
Memory read by BC subsystem. No response to Bus Request within timeout period. Looped back through receiver. Received Word last xmitted word. DMA/Write looped word to subsystem. Status-RT1, data, status-RT2 response to follow receive, transmit, commands.
ERROR SIGNAL
BC waits for Grant (no 1553 timing error) LOOPERR User Defined (See definitions in STATUS/DATA WORD below) TIMEOUT EOM STATERR STATERR Broadcast Mask not set (See BC Control Word) STATERR BC waits for Grant. MSGERR Status Word response: STATERR MSGERR and EOM MSGERR and EOM DMA/memory write (for each) MSGERR
PIN
-
46 -
STATUS WORD No Status Received within 15.5S RT Address Mismatch Error Flag(s) Set Broadcast Received bit Set
NODT timeout Command RTU Address Status Word RTU Address Status Word Response from RT: Error Condition Response to Transmit Status Word mode command may allow this, all others ERROR.
4 57 68 68
68
DATA WORD Handshake Failure Transmit Command Receive Command Data Received from RTU Less than word count Greater than word count Data after Status Set (all extra words) FORMAT ERROR
No subsystem response to Bus Request. Data lost: Word Count fails. 1553 transmission gap.
30 68 4 30
Transmit Command (RTU response) More data received than requested. Transmit Command: data words received after status to subsystem.
30
-
Notes: (1) LOOPERR is a .5S pulse which occurs near DMA handshake for loop back word. (2) TIMEOUT is a 40/160nS pulse which occurs 19.5S 0.5S after the mid-bit parity of the last word onto the bus. (3) STATERR is a 120/166nS pulse which occurs during the status word DMA handshake. (4) MSGRR is a 40/160nS pulse which occurs approximately 100nS before INCMD goes high. It is triggered by NODT going inactive (i.e., low word count).
Table 4 - BC Error Handling
RTU Response The addressed RTU(s) must respond (to non-broadcast commands) within a timeout period as shown in Figures 7, 8, and 9. Figures 10 and 11 illustrate the BC Mode Code Timing. Status and data words received from the 1553 port are transferred to the subsystem via a handshake and memory write operation for each (See Message Length Checking). BC Status/Error Handling Message transfer errors are indicated using the TIMEOUT, MSGERR, LOOPERR and STATERR BC status outputs (pins 4, 30, 46 and 68 respectively). Additional error detection methods include user evaluation of status, data and (long) loop words and/or use of the 1553B dual redundant mode codes. Note that certain error conditions not reflected in the current Status Word (SW) can occur; Broadcast CMD RT-status and post RT status response may be
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accessed via the Transmit Status Word mode command. Transmit Bit Word. Additional status informa tion is generated by an RTU (CT2565 for each transfer in the form of a BIT word). This word may be accessed by the BC using the TRANSMIT B-I-T WORD mode command. See RTU Error Handling and Mode Code sections). Message Length Checking. The BC stores the command word, word-count field in an internal register. By decrementing this register following each data word transfer (See BC Memory Read/Write Timing), the BC can detect an incorrect message length. For a description of the possible BC error, indicators occurring during each stage of message transfer read from left to right in Table 4. For a description of the possible causes of errors within a transfer, read from right to left.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
t1 BUSREQ (19) t2 BUSGRNT (45) t4 BUSACK (59) t3
HSFAIL (5)
TRI-STATE
SYMBOL
t1 t2 t3 t4
DESCRIPTION BUSREQ pulse width BUSREQ to BUSGRNT delay BUSGRNT pulse width BUSGRNT to BUSACK delay
MIN
867 0 166 50
MAX
1667 800 200
UNITS
ns ns ns ns
Figure 5 - BC Handshake Timing
BUSACK (59) t1 OE (18) t7 WR (44) t2 CS (17) t4 t5 ADRINC (49) t3 D0 - D15
DATA VALID
t9
t8 t9 t5 t10
DATA VALID
t6
t6
MEMORY READ
MEMORY WRITE
CYCLE
Read
SYMBOL
t1 t2 t3 t4 t5 t6
DESCRIPTION BUSACK to OE delay OE to CS delay Data setup time CS (OE) pulse width CS to ADRINC delay ADRINC pulse width BUSACK to WR delay WR to CS delay CS and WR pulse width Data valid setup
MIN
650 80 150 100
MAX
25 25 250 680 25 166 378 25 175 -
UNITS
ns ns ns ns ns ns ns ns ns ns
Write
t7 t8 t9 t10
Figure 6 - BC Read/Write Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
1553 BUS
50 200 ns
CMD
RTA
P DATA
P
STAT 10.750.75s
RTA
P
BC START (41) INCMD (9)
330 700 ns 2s 166s
HANDSHAKE (REQ, GRNT, ACK)
4s
43.50.5s
240.5s
MEM-READ (CS, OE, ADRINC) MEM-WRITE (CS, WR, ADRINC) D0 - D15 NODT (71) LWORD (29) STATERR (68) EOM (57) OUTPUTS
CLT CMD DATA 7.50.5s 5.50.5s 5.50.5s 5.5s TYP 440.5s LOOP STAT 7.50.5s
120 166 ns
200 500 ns 166 332 ns
200ns CHA/CHB LATCHED
Notes for Figures 7-9 T/R and HSFAIL are static at logic "1" in BC mode. All timing is typical unless otherwise noted.
Figure 7 - BC Receive One Word Command Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
1553 BUS
50 200 ns
CMD
RTA
P 10.750.75s
STAT
RTA
P DATA
P
BC START (41)
330 700 ns
INCMD (9)
166s
HANDSHAKE (REQ, GRNT, ACK) MEM-READ (CS, OE, ADRINC) MEM-WRITE (CS, WR, ADRINC) D0 - D15 NODT (71) LWORD (29)
CLT CMD (a) 5.50.5s
300.5s
200.5s
200.5s
LOOP 7.50.5s (B) (a)
STAT
DATA (B)
150ns (NOM)
50.5s
STATERR (68) EOM (57) OUTPUTS
120 166 ns 200ns CHA/CHB LATCHED MESS ERR. EX: LOW WD COUNT
200 500 ns
100ns 40 160 ns
Figure 8 - BC Transmit One Word Command Timing
1553 BUS
CMD RTA RX P RTB TX P STAT RTB P DATA P STAT RTA P
BC START (41)
330 700 ns
INCMD (9)
2s
HANDSHAKE (REQ, GRNT, ACK) MEM-READ (CS, OE, ADRINC) MEM-WRITE (CS, WR, ADRINC) D0 - D15 NODT (71) LWORD (29)
CTL CMD CMD LOOP 7.50.5s 5.50.5s 50.5s STAT DATA 7.50.5s 5.50.5s 150ns (NOM) 5.50.5s STAT 7.50.5s
STATERR (68) EOM (57)
200 500 ns
120 166 ns
Figure 9 - BC RT - RT Transfer Timing
10
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
1553 BUS INCMD (9) BUSREQ (19) ADRINC (49) D0 - D15 LWORD (29) EOM (57)
CTL CMD
CMD
RTA
P
STAT
RTA
P DATA
LCMD
P
70/80s 900ns
80/166ns LOOP STAT 5.00.5s LCMD
400/500ns
Figure 10 - BC Mode Code Transmit Last Command (10010) Timing
1553 BUS INCMD (9) BUSREQ (19) ADRINC (49) D0 - D15 LWORD (29) EOM (57)
CTL CMD
CMD
RTA
P
STAT
RTA
P
50/80sec 900ns 80/166ns LOOP 40/60sec STAT
400/500ns
Notes: All timing is typical unless otherwise noted.
Figure 11 - BC Mode Code Transmit Status Word (00010) Timing
RTU Operation Each RTU is assigned a unique address on the 1553 bus. It processes commands issued by the BC to its address or through Broadcast commands. Upon receipt of a valid command in the RTU mode, the CT2565 will attempt to (1) transfer 1553 data received to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status information to 1553, or (4) set status conditions. All data block transfers are accompanied by a 1553 Status Word. Figure 12 details a RTU single message transfer.
RTU Address RTU Address pins 33-34 and 72-74 and Address Parity pin (odd parity) should be programmed to a unique RTU (1553) address. These inputs have internal pull-ups and will default a high state if left unconnected. The CT2565 will not respond if odd parity is compromised (See Error Handling). RTU Initialization Initialize the CT2565 as an RTU per Table 2. Upon receipt of valid command word from the serial bus (RTU addressed or broadcast CMD), the CT2565 will pulse NBGRNT (New Bus Grant) pin 42 low.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
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COMMAND WORD
CMD WORD RECEIVED FROM 1553 NO WORD VALIDATION YES NO RT ADDR YES SSU BUSY NO STATUS TO 1553
DATA WORD(S)
A
RX CMD
YES
DATA FROM 1553
RT-RT TXFER YES STOP RT-RT
WORD VALIDATION STOP
STATUS TO 1553 WORD COUNT LATCHED T/R BIT LATCHED STATEN PULSED MODE CODE PULSE (MODE CODE ONLY) MORE DATA?
HANDSHAKE (DMA)
HS FAIL
NO
MEMORY WRITE DATA WORD TO SSIU
YES
CMD ILLEGALIZED ? NO HS FAIL
YES HANDSHAKE (DMA)
STATUS TO 1553
INCREMENT MEM ADDR OUTPUT
MEMORY READ STATEN PULSED STOP STOP HANDSHAKE (DMA) DATA TO 1553 HS FAIL STATEN PULSED DATA WORD FROM SSIU MORE DATA? INCREMENT MEM ADDR OUTPUT NO STATUS TO 1553 YES
SOM PULSED SHORT LOOP SHORT LOOP
NO
DATA EXPECTED ? YES A
STOP
END OF MESSAGE PULSED
STOP
Notes: (1) Steps marked with " _ _ _" indicates operation is transparent to user. (2) Steps marked with " ___" indicates user interaction required.
Figure 12 - RTU Single Message Transfer Flow Diagram
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Mode Code Illegalization (Optional) The word count and TX/RX pins will be latched 800ns (typ) after the falling edge of NBGRNT (See Figure 13, RTU Command Word Handling). Table 5 lists the CT2565 pins associated with mode code illegalization. If the current command is a mode code, LMC (pin 55) will go high. Mode codes can be illegalized, using an external PROM (<200ns access time recommended), by setting ILLCMD low after the NBGRNT flag. This will set the message error (status word) and illegal Mode Code (BIT word) bits followed by transmission of the status word. Using the method, mode commands can be "auto-screened" without interrupting subsystem operation. For a complete list of mode codes, refer to Table 8.
NBGRNT (42) t1 LMC (55) t2 WC0-4 T/R (15) t4 ILLCMD (48) t5 INCMD (9) BUSREQ (19) BUSACK (59) t3
Table 5 - Mode Code Illegalization
PIN # 51 12 52 13 53 15 SYMBOL WC0 WC1 WC2 WC3 WC4 T/R DESCRIPTION Word Count LSB Word Count 1 Word Count 2 Word Count 3 Word Count MSB TX/RX
Note: A word count field of all 0's indicates 32 data words; all 1's = 31 words.
VALID UNTIL NEXT VALID COMMAND WORD RECEIVED
LATCHED UNTIL NEXT VALID COMMAND WORD RECEIVED
t6 SOM (78)
t7 t8
D0 - D15 t9 STATUS INPUTS
DBACCEPT, SSFLAG, SVCREQ, SSER and SSBUSY INPUTS
CMD VALID
LATCHED
SYM
Illegalize t1 t2 t3 t4 Legal t5 t6 t7 t8 Status Inputs t9
DESCRIPTION NBGRNT pulse width NBGRNT to LMC delay LMC to WC-T/R latch LMC to ILLCMD latch NBGRNT to INCMD delay BUSACK to SOM delay SOM pulse width CMD VALID setup NBGRNT low to status latch
MIN
151 500 60 -
TYP
200 1.0 166 166 -
MAX
181 667 333 1.5 100 3
UNITS
ns ns ns ns s ns ns ns s
Note: Memory read/write signals CS, OE, and ADRINC remain static at logic "1".
Figure 13 - RTU Command Word Handling/Status Inputs
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RTU Commands A command word transfer will be initiated by the CT2565 after the rising edge of NBGRNT (See Figure 14). In order to allow the command word to be stored in user-defined memory space (separate from data), no memory write operation (CS, WR, ADRINC outputs) will be initiated following the usual DMA-type handshake; a Start Of Message (pin 78: SOM low) pulse indicates that the CMD word is currently valid on the data bus. Note that commands are named from the BC point-of-view (i.e., a TRANSMIT CMD dictates that the addressed RTU must transmit data). Transmit CMD (RT-BC) If the subsystem is available (pin 47: SSBUSY high): following transmission of the status word, the CT2565 will initiate a handshake/memory-read respectively for the total number of (data) words defined by the Command Word-word count field. Figure 15 shows the RTU Read/Write Timing. Note that possible data word transfer and short-loop test errors will be reflected in the following status word/bit word. A low on the SSBUSY input will set the corresponding status word flag, and no data transfer will be requested (BUSREQ low) following transmission of the status word. Receive CMD (BC-RT). A DMA handshake will be initiated for each word received over the 1553 data bus (See Figure 16). If successful, the respective handshake will be followed by a corresponding memory write. Transfer errors such as handshake timeout or SS BUSY will not terminate transfer attempts for the remaining data words, error flagging or status word transmission. RTU(b)-RTU(a) (Transmit/Receive). An RT-RT TRANSFER/CONDITION
COMMAND WORD Invalid Word Format Invalid Command (format error) Handshake Failure Illegal Mode Command RT-RT Transfer Response Timeout Address mismatch DATA WORD Handshake Failure Transmit Command Receive Command Number Transmitted (2)
transfer will appear to both RTU subsystems as a standard transmit or receive command except: (1) transmission of the data block will not be continuous with that of the receive CMD, and, (2) upon detection of a command-sync field following the receive CMD, RTU(a) will recognize an RT-RT transfer and store the transmit CMD-address field for comparison with the address field of the following (RTU(b) status) word (See Figures 17 and 18). If a mismatch is detected, RTU(a) will issue a message error. The transmitting RTU will respond as in an RT-BC Transmit CMD. RTU Status/Error Handling Message transfer errors are indicated using the TIMEOUT, HSFAIL, MSGERR and LOOPERR RTU-status outputs (pins 4, 5, 30 and 46 respectively). Additional error detection mechanisms available include status input manipulation (below) and evaluation of the status and BIT words (See BIT Word). Table 6 describes error handling mechanisms related to each stage in a message transfer (reading left to right) as well as noting errors associated with a specific CT2565 status output (reading right to left). Short Loop Test. The last word to be transmitted in a given message transfer (Status word, BIT word or Data word) is stored in a CT2565 internal register. As this word is transmitted to the 1553 bus, it is "looped back" through the active receiver channel for auto-RTU, "SHORTLOOP" verification. A LOOPERR low pulse indicates a mismatch between the stored and looped words. Note that short loop testing is initiated for all RTU transfers except a Broadcast transfer.
DESCRIPTION
Sync, bit count invalid. Operation disagreement (e.g. Broadcast and Transmit bits set) BUSREQ to BUSGRNT timeout Subsystem set ILLCMD (pin 48). (Transmit) Command to Status Word time. Transmit Command Address address.
ERROR SIGNAL
None; input ignored MSGERR (also; SW bit) HSFAIL, suppress SOM, continue SW message error bit set TIMEOUT (transmitting RT) (also; MSGERR bit) MSGERR (Receiving RT) (also; MSGERR bit) HSFAIL (1) Continue message transfer INCMD high, EOM MSGERR (3) (SW bit) MSGERR after validation (no transfer) SW and BITWord also set. LOOPER (also sets TerFlag bit).
PIN
30 5 78
4 30
Status Word
BUSREQ to BUSGRNT timeout (Continue) (Message terminated) Low data word-count received. High data word count
5 9,57 30 30
LOOP WORD Short Loop Long Loop
Looped back through receiver. Received word to last xmitted 1553 word. (BC only)
46
Notes: (1) The HSFAIL low output is reset (high) at the start of the next message transfer (NBGRNT low). (2) The subsystem can use the status input pins (SW) to report incorrect word count type errors. (3) MSGERR set 7.5S after last mid parity bit of last data word.
Table 6 - RTU Error Handling
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
BUSREQ (19) t2 BUSGRNT (45) t3 BUSACK (59)
t1
HSFAIL (5)
SYMBOL
t1 t2
DESCRIPTION BUSREQ pulse width BUSGRNT delay CMD WORD TX DATA WORD RX DATA BUSGRNT to BUSACK delay
MIN
667 0 0 0 40
MAX
1.5 15.5 2.33 166
UNITS
ns s s s ns
t3
Note: HSFAIL will go low following a BUSREQ to BUSGRNT timeout.
Figure 14 - RTU Handshake Timing
BUSACK (59) t1 OE (18) t7 WR (44) t2 CS (17) t4 t5 ADRINC (49) t3 D0 - D15
VALID
t4
t8 t9 t5
t6
t10
VALID
MEMORY WRITE
MEMORY READ
CYCLE
Read
SYMBOL
t1 t2 t3 t4 t5 t6
DESCRIPTION BUSACK to OE delay OE to CS delay Data setup time CS, OE and BUSACK pulse width CS to ADRINC delay ADRINC pulse width BUSACK to CS delay WR to CS delay CS and WR pulse width Data valid setup prior to leading edge of WR
MIN
80 150 60
TYP
500 166 -
MAX
25 25 250 25 166 225 25 180 100
UNITS
ns ns ns ns ns ns ns ns ns ns
Write
t7 t8 t9 t10
Figure 15 - RTU Read/Write Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Use of Status Word The status word may be captured by the subsystem as it is transmitted to the 1553 port by pulsing BUFENA (pin 58) low during STATEN (pin 3: 520ns low pulse). Data becomes valid approximately 50ns after the falling edge of BUFENA. This corresponds with all non-broadcast message transfers and the TRANSMIT STATUS WORD mode command. Note that the status word may be transmitted prior to an error condition (See Transmit CMD). These conditions will be indicated in the "next" status word and may be monitored if the BC requests the SW before it is altered (See Mode Commands). Subsystem Control The CT2565 allows the subsystem total control over the status word flags using the inputs indicated in Table 7. BIT Word The BIT Word (Built-In-Test) becomes available in response to a TRANSMIT BIT WORD mode command and provides additional status information (See Figure 19) to that provided by the status word. The subsystem may capture the BIT word on the parallel data bus by pulsing BUFENA
1553 BUS
CMD RTA RCV P DATA (16 BITS) P
(pin 58) low during BITEN (pin 43: approximately 520ns low pulse). Data Becomes valid approximately 50ns after the falling edge of BUFENA. Like the status word, the BIT word cannot be altered by the subsystem. PIN # 6 7 8 SYMBOL DBACCEPT SSFLAG SVCREQ DESCRIPTION RT accepts BC operation responsibility (See Table 2). Transmitted data may be invalid sets SSFLAG bit. Service Request; see Transmit Vector mode command. RTU fault exists: sets TERMINAL FLAG bit. Subsystem cannot service 1553 request at this time. Mode command subsystem illegalization: Sets MSGERR bit, doesn't suppress status word.
10 47 48
SSER SSBUSY ILLCMD
Table 7 - Subsystem Control of RT-Status
STAT RTA P 7.50.5s 5.50.5s 4.50.5s
REF 10.750.75s 7.50.5s
3.40.5s
NRGRNT (42)
0.5s
BCSTRCV (75)
1.5s
3.20.5s
INCMD (9)
3.9s
HANDSHAKE (REQ, GRNT, ACK) SOM (78) MEM-WRITE (CS, WR, ADRINC) D0 - D15
5.50.5s CMD DATA STAT
NODT (71)
4s
STATEN (3)/ BUFFENA (58) EOM (57)
667ns
400ns
WC 0-4 T/R (15)
166ns
CHA/CHB (16)
Note: All timing is typical unless otherwise noted.
Figure 16 - RT Receive Command Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
1553 BUS
CMD
RTA
TX
P 10.750.75s 7.50.5s 3.40.5s
STAT
RTA
P DATA
(16 BITS)
P 7.50.5s 4.50.5s
5.50.5s 1.00.2s
NRGRNT (42) ILLEGALIZE
1.5s LMC ILLCMD
INCMD (9) HANDSHAKE (REQ, GRNT, ACK) SOM (78) MEM-READ (CS, OE, ADRINC) D0 - D15
5.50.5s CMD STAT DATA
NODT (71)
4s
STATEN (3)/ BITEN (43) EOM (57)
667ns
50020ns
50020ns
165ns
WC 0-4 T/R (15)
166ns
CHA/CHB (16)
Notes: (1) All timing is typical unless otherwise noted. (2) BITEN only occurs when XMIT BIT WD mode code command is received (Handshake and read/write signals are not generated in this case).
Figure 17 - RT Transmit Command Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
1553 BUS
CMD RTA RCV P CMD RTB
TX
P 10.750.75s 7.50.5s
STAT RTB P DATA
P REF 10.750.5s 7.50.5s
STAT RTA P 7.50.5s 4.50.5s
(16) BITS
3.40.5s
NRGRNT (42) ILLEGALIZE INCMD (9)
2.3s LMC ILLCMD 1.5s
HANDSHAKE (REQ, GRNT, ACK) SOM (78) MEM-READ (CS, WE, ADRINC)
RCV
D0 - D15 NODT (71)
CMD 5.50.5s 5.50.5s
DATA
STAT
450ns
STATEN (3)/ BITEN (43) EOM (57) TIMEOUT (4)
(TIMEOUT ERROR) 19.5s 400ns
500ns
400ns (NO TIMEOUT)
330ns Note: All timing is typical unless otherwise noted.
Figure 18 - RT- RT Transfer Timing
15 87 0
SET TO "0" SET TO "0" CHAN B XMITTER TIMEOUT CHAN A XMITTER TIMEOUT CHAN B LOOP TEST FAILURE CHAN A LOOP TEST FAILURE CHAN B XMITTER SHUTDOWN CHAN A XMITTER SHUTDOWN NON-MODE BROADCAST CMD TO XMIT MESSAGE HIGH WORD COUNT MESSAGE LOW WORD COUNT ILLEGAL MODE CODE OR ILLEGAL BROADCAST WITH MODE CODE MODE CODE OR T/R ERROR CHAN A/B LOOP TEST FAILURE HANDSHAKE FAILURE CHAN A/B XMITTER TIMEOUT
Notes: (1) Bits 0-2 and 10-13 are latched and only cleared by a mode reset command or a master RESET. (2) Bits 3-7 are cleared at the start of each new message and updated at the end of the message. They reflect the present command word. (3) Bits 8-9 are set by the mode command for Transmitter Shutdown and are cleared by the mode command for Override Transmitter Shutdown, Reset RT or a master RESET.
Figure 19 - Bit Word
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
MT Operation In the MT mode, the CT2565 captures all valid transmissions on both channels of the 1553 bus, allowing the user to monitor bus activity. Each word is transferred to the subsystem along with an identification for interpretation of the 1553 data stream. MT Initialization Initialize the CT2565 for MT operation per Table 2. The CT2565 will remain in an idle state until BCSTART (pin 41) is pulsed low. Figure 21 illustrates MT operation. Valid words received by the CT2565 are transferred to the subsystem along with an identification Word by a single DMA handshake with two memory-write operations shown in Figure 22, MT Transfer Timing. Since the decoder will reject words based on sync field errors and/or errors in the first 2 non-sync bits, these words will not be processed further (i.e., the subsystem will receive no indication of the receipt of this word).
15
GAP TIME WORD TRANSFER LOGIC "1" LOGIC "1" VALID WORD COMMAND SYNC CH A/B WORD GAP SET TO "0"
START
INITIALIZATION (START-UP ONLY)
START MT OPERATION
1553 BUS ACTIVITY
DECODER CHECK SYNC + 2 BITS
87
0
YES ERROR ? NO NODT LOW
YES
DMA
MEMORY WRITE 1553 INPUT
INCREMENT MEM ADDR
NAME
GAP TIME
Definition
NODT low time. 2MHz Clock allows 500ns increments to 128s (remains static at FF on overflow). Logic "1" indicates successful transfer to subsystem. Indicates successful transfer (See bit 7) Reset (1) indicates Manchester error, Parity error, Low Bit Count and/or Status sync field. Logic "1" indicates Command or Status sync field. Logic "0" indicates data sync. Logic "1" if word received on 1553 bus Channel B. Set (0) if current word was received at least 2s after receipt of previous word (parity to mid-sync).
Notes: (1) Steps marked with " _ _ _" indicates operation is transparent to user. (2) Steps marked with " ___" indicates user interaction required.
MEMORY WRITE IDENTIFICATION WORD
INCREMENT MEM ADDR
WORD TRANSFER WORD TRANSFERRED VALID WORD
COMMAND SYNC
Figure 21 - MT Operation Flow Chart
CHAN A/B WORD GAP
Note: Subsystem should clear entire memory prior to start of MT operation.
Figure 20 - Identification Word
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Simultaneous Transmission Transmissions appearing simultaneously on alternate 1553-bus channels will be captured by CT2565 sequentially providing that each BUSREQ is answered by the subsystem with a BUSGRNT within the handshake timeout period. RESET Signal Pulsing RESET low will suspend MT operation by (1) INCMD goes high (EOM goes low on the rising edge) and (2) the CT2565 enters an idle state. MT operation may be restored by pulsing BCSTART low (above) or another mode of operation may be selected (See Table 2).
Handshake Failure Note that a handshake failure will abort the current transfer. Monitoring will resume upon receipt of a valid word on the 1553 bus. MODE CODES Nine of the 13 available, dual redundant mode codes are handled by the CT2565 without user intervention. Of the four remaining codes, Dynamic Bus Control and Synchronize (no data) require subsystem notification. The remaining two mode codes, Transmit Vector Word and Synchronize (with data) involve data transfer with the subsystem. Mode command illegalization and handling are detailed in the RTU Operation section and listed in Table 8.
BUSREQ (19) t1 BUSGRNT (45) t2 t3 BUSACK (59) t4 WR (44) t5 CS (17) t8 ADRINC (49) t7 D0 - D15 DATA VALID t10 ID-WORD VALID t6 t8 t9 t6 t6
CYCLE
Handshake
SYM
t1 t2 t3
DESCRIPTION BUSREQ to BUSGRNT delay BUSGRNT pulse width BUSGRNT to BUSACK delay BUSACK to WR delay WR to CS time WR and CS pulse width DATA VALID setup CS to ADRINC delay ARINC pulse width ID WORD VALID setup
MIN
0 166 ? 320 150 80 -
TYP
330 166 -
MAX
800 ? 370 25 175 50 25 166 100
UNITS
ns ns ns ns ns ns ns ns ns ns
Write Only
t4 t5 t6 t7 t8 t9 t10
Figure 22 - MT Transfer Timing
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
DYNAMIC BUS CONTROL (00000) MESSAGE SEQUENCE = DBC * STATUS The CT2565 responds with status. If the subsystem wants control of the bus, it must set DBACC within 2.5us after NBGRT. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (Bit Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word). SYNCHRONIZE WITHOUT DATA WORD (00001) MESSAGE SEQUENCE = SYNC * STATUS The CT2565 responds with status. If sent as a broadcast, the broadcast receive bit will be set and status response suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word). TRANSMIT STATUS WORD (00010) MESSAGE SEQUENCE = TRANSMIT STATUS * STATUS The status and BIT word registers are not altered by this command and contain the resulting status from the previous command. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (S/W), Illegal Mode code, T/R Error (BIT Word). INITIATE SELF-TEST (00011) MESSAGE SEQUENCE = SELF TEST * STATUS The CT2565 responds with a status word. If the command was broadcast, the broadcast received bit is set and status transmission suppressed. Short-loop test is initiated on the status word transmitted. If the test fails, an RT fail flag is generated. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word). 5. Faulty Test. Bits set: terminal flag (SW), A/B Loop Test Fail, Current 1553 Bus (A or B) Loop Test Fail (BIT Word).
TRANSMITTER SHUTDOWN (00100) MESSAGE SEQUENCE - SHUTDOWN * STATUS This command is only used with dual redundant bus systems. The CT2565 responds with status. At the end of the status transmission, the CT2565 inhibits any further transmission from the dual redundant channel. Once shutdown, the transmitter can only be re-activated by Override Transmitter Shutdown or RESET RT commands. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word).
Table 8 - Mode Codes
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
OVERRIDE TRANSMITTER SHUTDOWN (00101) MESSAGE SEQUENCE - OVERRIDE SHUTDOWN - STATUS This command is only used with dual redundant bus systems. The CT2565 responds with status. At the end of the status transmission, the CT2565 re-enables the transmitter of the redundant bus. If the command was broadcast, the broadcast received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word). INHIBIT TERMINAL FLAG BIT (00110) MESSAGE SEQUENCE - INHIBIT TERMINAL FLAG * STATUS The CT2565 responds with status and inhibits further internal or external setting of the terminal flag bit in the status register. Once the terminal flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT command. If the command was broadcast, the broadcast received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
OVERRIDE INHIBIT TERMINAL FLAG BIT (00111) MESSAGE SEQUENCE - OVERRIDE INHIBIT TERMINAL FLAG * STATUS The RTU responds with status and reactivates the terminal flag bit in the status register. If the command was broadcast, the broadcast received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word). RESET REMOTE TERMINAL (01000) MESSAGE SEQUENCE - RESET REMOTE TERMINAL * STATUS The CT2565 responds with status and internally resets. Transmitter shutdown, mode commands, and inhibit terminal flag commands will be reset. If the command was broadcast, the broadcast received bit is set and the status word is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word). RESERVED MODE CODES (01001-01111) MESSAGE SEQUENCE = RESERVED MODE CODES * STATUS The CT2565 responds with status. If the command is illegalized through an optional PROM, the message error bit is set and only the status word is transmitted. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), Illegal Mode Code (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
Table 8 - Mode Codes (continued)
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
TRANSMIT VECTOR WORD (10000) MESSAGE SEQUENCE - TRANSMIT VECTOR WORD * STATUS VECTOR WORD The CT2565 transmits a status word followed by a vector word. The contents of the vector word (from the subsystem) are enabled onto DBO-DB15 with BUSREQ after the command transfer (same as data word in a normal transmit command). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW) High Word Count (BIT Word). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error, Low Word Count (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
SYNCHRONIZE WITH DATA WORD (10001) MESSAGE SEQUENCE - SYNCHRONIZE DATA WORD * STATUS The data word received following the command word is transferred to the subsystem. The status register is then enabled and its contents transferred onto the data bus and transmitted. If the command was broadcast, the broadcast received bit is set and status transmission is suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), Low Word Count (BIT Word). 3. Command followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count (BIT word). 4. Command T/R bit Set to One. No status response. Bits set: message error (SW), T/R Error, High Word Count (BIT Word). 5. Command, T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), High Word Count, T/R Error (BIT Word).
TRANSMIT LAST COMMAND (10010) MESSAGE SEQUENCE = TRANSMIT LAST COMMAND * STATUS LAST COMMAND The status and BIT word registers are not altered by this command. The SW contains the status from the previous command. The data word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND). ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, (SW), Illegal Mode Code T/R Error (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
TRANSMIT BIT WORD (10011) MESSAGE SEQUENCE - TRANSMIT BIT WORD * STATUS BIT WORD The CT2565 transmits a status word followed by the BIT word . When activated, BITEN allows the subsystem to latch the BIT word on the parallel data bus. The BIT word is not altered by this command; however, the next SW will reflect errors in this transmission. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW). 3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error, Low Word Count (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
Table 8 - Mode Codes (continued)
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
SELECTED TRANSMITTER SHUTDOWN (10100) MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS The data word received is transferred to the subsystem and status is transmitted. If the command was broadcast, the broadcast received bit is set and status transmission suppressed. Intended for use with RTs with more than one dual redundant channel. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word). 3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code (BIT Word). 4. Command T/R bit Set to One. No status response. Bits set: message error (SW), Illegal Mode Code, High word count (BIT Word). 5. Command T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, High Word Count (BIT Word).
OVERRIDE SELECTED TRANSMITTER SHUTDOWN (10101) MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS The data word received after the command word is transferred to the subsystem. If the command was broadcast, the broadcast received bit is set and status transmission suppressed. ERROR CONDITIONS 1. Invalid Command. No response, command ignored. 2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code (BIT Word). 3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word). 4. Command T/R bit Set to One. No status response. Bits set: message error (SW), Illegal Mode Code, High Word Count (Bit Word). 5. Command T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, High Word Count, T/R (BIT Word).
RESERVED MODE CODES MESSAGE SEQUENCE = RESERVED MODE CODE (T/R = 1) * STATUS RESERVED MODE CODE (T/R = 0) * STATUS The CT2565 responds with status. If the command was broadcast, the broadcast received bit is set and status transmission suppressed. ERROR CONDITIONS (T/R = 1) 1. Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word). ERROR CONDITIONS (T/R = 0) 1. Invalid Command. No response, command ignored. 2. Command not Followed by Contiguous Data Word. No status response. Bits set: message error (SW), High word Count, Illegal Mode Code (BIT Word). 3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word).
Table 8 - Mode Codes (continued)
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 9A - Pin Function Table (78 Pin DDIP)
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Symbol RT/BC MT STATEN TIMEOUT HSFAIL DBACCEPT SSFLAG SVCREQ INCMD SSER TESTOUT WC1 WC3 TXINH B T/R CHA/CHB CS OE BUSREQ +5V DB0 DB2 DB4 DB6 DB8 DB10 DB12 DB14 LWORD Description Mode Select input - logic "1" for RT mode, logic "0" for BC mode. Monitor mode enable. When unit is operating as a BC, a logic "0" will select monitor mode. Output signal in RT mode that indicates status word is being transferred on the internal bus. Indicates No Response Timeout has occured during BC and RTU (RT to RT transfer). Output in RT mode indicating the DMA transfer did not occur in time to allow proper operation on the 1553 bus. Input signal used to set DBACCEPT bit in status register for response to a valid mode command on the 1553 bus. Input which controls the SSFLAG bit in the status register. Input which controls the service request bit in the status word. Output signal indicating the RT is currently in a message transfer sequence. Input which controls the subsystem error bit in the status register. Factory test point. Do not connect. WC bit 1 - latched output of command word. WC bit 3 - latched output of command word. Transmitter inhibit output for channel B. Output indicating T/R bit of current command word in RT mode. Output indicating current selected channel (0 = Channel A). Chip Select output for subsystem memory control. Output Enable output for subsystem memory control. Output signal used to initiate transfer to/from subsystem. +5 Volt DC input. Least significant bit - 16 bit parallel data bus. Bit 2 of data bus. Bit 4 of data bus. Bit 6 of data bus. Bit 8 of data bus. Bit 10 of data bus. Bit 12 of data bus. Bit 14 of data bus. Last word output during BC mode indicates last data word of the current message transfer has been transferred on the parallel bus.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 9A - Pin Function Table (78 Pin DDIP) (continued)
Pin # 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Symbol MSGERR TXDATA A RXDATA A RTADP RTAD1 RTAD3 RESET TXDATA B RXDATA B 12MHz GROUND BCSTART NBGRNT BITEN WR BUSGRNT LOOPERR SSBUSY ILLCMD ADRINC CHASSIS WC0 WC2 WC4 TXINH A LMC TESTIN EOM BUFENA Description Output signal which indicates an error occurred during the current message sequence. Bipolar serial data output to positive input of bus transceiver. Bipolar serial input from negative output of bus transceiver. Parity bit input for RT address. Bit 1 of RT address input. Bit 3 of RT address input. System reset input - resets all inputs in module. Bipolar serial data output to negative input bus transceiver. Bipolar serial data input from positive output of bus transceiver. 12MHz TTL clock input. Signal ground. Cycle enable input Logic "0" initiates bus controller message transfer operation. New bus grant output from RT indicates beginning of message transfer sequence. Built in Test enable output indicates RT is transferring BlT word on internal 16 bit bus. Write enable output for control of subsystem memory. Bus request input in response to DTREQ. Allows BC/RT to transfer data to subsystem. Loop error output. Logic "0" indicates failure of loop back transmitted data. Subsystem busy input for RT status word. Illegal command input to RT, used to block RT response to an illegal command. Increment output pulse. Goes LOW at the completion of each word transfer to/from subsystem. Can increment external address counter. Frame ground electricity isolated from signal ground LSB of current command word count field. Bit 2 of word count field. Bit 4 of word count field. Transmitter inhibit output signal for Channel A. Latched Mode Command. Logic "1" indicates current word command is a mode code word, WC0-WC4. Factory test point. Do not connect. End of message output. Logic "0" occurs when BC/RT message is completed. Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem must read bit or Status words. Enables internal 16 bit bus onto subsystem bus.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 9A - Pin Function Table (78 Pin DDIP) (continued)
Pin # 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Symbol BUSACK DB1 DB3 DB5 DB7 DB9 DB11 DB13 DB15 STATERR TXDATA A RXDATA A NODT RTAD0 RTAD2 RTAD4 BCSTRCV TXDATA B RXDATA B SOM Description Bus acknowledge output. LOW during DMA Handshake, in response to BUSGRNT. Bit 1 of 16 bit parallel bus. Bit 3 of 16 bit parallel bus. Bit 5 of 16 bit parallel bus. Bit 7 of 16 bit parallel bus. Bit 9 of 16 bit parallel bus. Bit 11 of 16 bit parallel bus. Bit 13 of 16 bit parallel bus. Bit 15 of 16 bit parallel bus. BC output indicates one or more bits set or address mismatch in a received status word. Bipolar serial data output to negative input of bus transceiver. Bipolar serial data input from positive output of bus transceiver. No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front end is active. LSB of 5 bit RT address. Bit 2 of RT address. Bit 4 of RT address. Broadcast receive. Logic "0" means the current command was a broadcast command. Bipolar serial output to positive input of bus transceiver. Bipolar serial input from negative output of bus transceiver. Start of message output indicates beginning of RT/BC message transfer sequence.
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SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 9B - CT2565 Pin Out Description (DDIP)
Pin #
1 2 3
Function
RT/BC
MT STATEN TIMEOUT HSFAIL DBACCEPT SSFLAG SVCREQ INCMD SSER TESTOUT WC1 WC3 TXINH B T/R CHB/CHA CS
Pin #
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
Function
GND BCSTART NBGRNT BITEN WR BUSGRNT LOOPERR SSBUSY ILLCMD ADRINC CASE GND WC0 WC2 WC4 TXINH A LMC TESTIN EOM BUFENA BUSACK DB1 DB3 DB5 DB7 DB9 DB11 DB13 DB15 (MSB) STATERR TXDATA A RXDATA A NODT RTAD0 RTAD2 RTAD4 BCSTRCV TXDATA B RXDATA B SOM
1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20
RT/BC
BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM
CT2565
MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR
OE
BUFENA BUSREQ BUSACK +5 Volt
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 12MHz SOM GND
21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
OE
BUSREQ + 5 Volt DB0 (LSB) DB2 DB4 DB6 DB8 DB10 DB12 DB14 LWORD MSGERR TXDATA A RXDATA A RTADP RTAD1 RTAD3 RESET TXDATA B RXDATA B 12MHz
DDIP Pin Connection Diagram, CT2565 and Pinout
Aeroflex Circuit Technology
28
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Table 10 - CT2565 Pin Out Description (FP)
Pin #
1 2 3
Function
N/C RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC2 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5V N/C
Pin #
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
Function
N/C GROUND SOM 12MHz RXDATA B RXDATA B TXDATA B TXDATA B BCSTRCV RESET RTAD4 RTAD3 RTAD2 RTAD1 RTAD0 RTADP NODT RXDATA A RXDATA A TXDATA A TXDATA A MSGERR STATERR LWORD DB15 (MSB) DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
N/C
RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5V N/C
N/C
CT2565FP
MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR
DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 12MHz SOM GROUND
N/C
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Flat Package Pin Connection Diagram, CT2566 and Pinout
Aeroflex Circuit Technology
29
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
2.100
1.870 Lead 1 & ESD Designator
.100 .110
Pin 1 Pin 2
1.900
.050 Pin 19 TYP Pin 20 Pin 59 Pin 41 .018 DIA TYP
.250 MAX
1.650 1.500
Pin 60 Pin 78 Pin 21 Pin 22 .100 TYP Pin 39 Pin 40
.250
1.800
Figure 23 - Plug In Package Outline
2.200 MAX .010 .002
Pin 42
.050 Pin 82
.015
.180 MAX
1.610 MAX Lead 1 & ESD Designator .400 MIN .095 (4 Places) 2.000 .050 Lead Centers 41 Leads/Side
Pin 41
.080
Figure 24 - Flat Package Outline
Aeroflex Circuit Technology
30
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number CT2565 CT2565-FP CT2565-001-1 CT2565-001-2 CT2565-201-1 CT2565-201-2 Screening Military Temperature, -55C to +125C, Screened to the individual test methods of MIL-STD-883 Per SMD DESC SMD # 5962-8858501XA 5962-8858501XC 5962-8858501YA 5962-8858501YC Package Plug in Flat Package Plug in Plug in Flat Package Flat Package
Specifications subject to change without notice
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) THE-1553 E-Mail: sales-act@aeroflex.com
31
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700

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